A demand for a panel with high resolution and low power consumption has been proposed constantly along with the development of a flat panel display. Low Temperature Poly-Silicon (LTPS) has been widely applied to a Liquid Crystal Display (LCD) and an Organic Light Emitting Diode (OLED) display due to its high mobility of electrons. In the LTPS technology, a Lightly Doped Drain (LDD) is commonly adopted to suppress leakage current rising abnormally. FIG. 1a and FIG. 1b illustrate schematic sectional views of a device in an existing method for forming an LDD area. As illustrated in FIG. 1a, after a buffer layer 102 and a poly-silicon layer 103 are formed in sequence on a substrate 101, a photo-resist layer 104 is applied on the poly-silicon layer 103 and patterned. An area of the poly-silicon layer 103, which is not covered by the photo-resist layer 104, is doped by an ion doping process, so that the area which is not covered by the photo-resist layer 104 can be subsequently doped for a second time into a heavily doped drain area. As illustrated in FIG. 1b, after the poly-silicon layer 103 is doped for the first time, a gate insulation layer and a gate metal layer are formed in sequence on the doped poly-silicon layer, and the gate metal layer is patterned to form a gate electrode 106. An injection area is defined using the gate electrode 106 as a mask through self-alignment of the gate electrode 106, and an area which is not covered by the gate electrode 106 is doped by an ion doping process, resulting in a lightly doped drain area 107 and a heavily doped drain area 108.
In summary, the LDD area has to be formed at present by two ion doping processes, thus complicating the preparation procedure, and it may not be easy to control the precision of a junction depth in the formed LDD area due to an error in alignment using the mask by two patterning processes.